Hardware operators for pairing-based cryptography
Dr. Jean-Luc Beuchat
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Abstract
Since their introduction in constructive cryptographic applications, pairings over (hyper) elliptic curves are at the heart of an ever increasing number of protocols. As they rely critically on efficient algorithms andimplementations of pairing primitives, the study of hardware accelerators became an active research area. In this talk, we describe a coprocessor for the reduced eta_T pairing introduced by Barreto et al. as an alternative means of computing the Tate pairing on supersingular elliptic curves. We prototyped our architecture on FPGAs. According to our place-and-route results, our coprocessor compares favorably with other solutions described in the open literature.
Jean-Luc Beuchat received his M.Sc. and his Ph.D. in computer science from the Swiss Federal Institute of Technology, Lausanne, in 1997 and 2001, respectively. He is an associate professor in the Graduate School of Systems and Information Engineering at the University of Tsukuba, Japan. His current research interests include computer arithmetic and cryptography.
